module regfile(
input [4:0] rr1, rr2, //read register1, read register2,
input [4:0] wr, //write register,
input [7:0] wd, //write data,
input wb, //write bit
input clk, //clock,

output [7:0] rd1, rd2 //read data1, read data2
); //regfile. 8-bit register, 32 registers

reg [7:0] r [31:0];

//initializing register value//
//because there is no 'addi' operation..//
initial begin
r[0]=0; r[1]=0; r[2]=0; r[3]=0; r[4]=0; //zero, at, v0, v1, a0
r[5]=0; r[6]=0; r[7]=0; r[8]=0; r[9]=0; //a1, a2, a3, t0, t1
r[10]=0; r[11]=0; r[12]=0; r[13]=0; r[14]=0; //t2, t3, t4, t5, t6
r[15]=0; r[16]=1; r[17]=16; r[18]=0; r[19]=0; //t7, s0, s1, s2, s3,
r[20]=0; r[21]=0; r[22]=0; r[23]=0; r[24]=0; //s4, s5, s6, s7, t8,
r[25]=0; r[26]=0; r[27]=0; r[28]=0; r[29]=0; //t9, k0, k1, gp, sp,
r[30]=0; r[31]=0; //fp, ra
end

assign rd1 = r[rr1];
assign rd2 = r[rr2];

always @ (negedge clk) begin
if(wb)
r[wr] = wd;
end

endmodule